TSMC began high-volume manufacturing on its 2nm (N2) node in early 2026. Capacity is booked through late 2026, Apple has secured more than 50 percent of initial allocation, and TSMC announced a 3 to 5 percent sub-5nm price hike that propagates through the AI chip cost stack. NVIDIA Rubin is reportedly on N3P rather than N2 for the first generation, leaving the marquee AI chip slot at N2 to AMD's Zen 6 and EPYC Venice. This page consolidates the customer allocation, capacity ramp, and pricing dynamics shaping AI silicon supply in 2026.
Key Findings
- TSMC 2nm (N2) entered high-volume manufacturing in early 2026 at Fab 20 in Hsinchu. The target wafer-out capacity is 60,000 wafers per month by Q4 2026, ramping further in 2027.
- Apple has booked more than 50 percent of N2 initial allocation for the A20 (iPhone 17 family) and M6 (Mac) silicon, the largest single-customer allocation on a TSMC leading-edge node since the original N3 ramp.
- AMD\u2019s Zen 6 and EPYC Venice are reported to use N2 starting in the second half of 2026, making AMD the most prominent CPU-side N2 customer.
- NVIDIA Rubin (the Blackwell successor for AI training) is reportedly on TSMC N3P for the first generation, with N2 reserved for a later refresh. The decision reflects N2 capacity constraints and the cost-performance tradeoff for large reticle-stitched chips.
- TSMC announced a 3 to 5 percent price increase across sub-5nm nodes effective FY2026, the first explicit price hike since the 2024 cycle. The increase reflects rising EUV mask, wafer, and assembly costs.
TSMC 2nm Customer Allocation (Initial 2026 Ramp)
| Customer | Product | Estimated Allocation Share |
|---|---|---|
| Apple | A20 (iPhone 17), M6 (Mac) | ~50-55% |
| AMD | Zen 6, EPYC Venice (H2 2026) | ~12-15% |
| Qualcomm | Snapdragon X next-gen | ~6-8% |
| MediaTek | Dimensity 9500 successor | ~6-8% |
| NVIDIA | Reserved for post-Rubin refresh | ~5-7% |
| Intel | Limited foundry use | ~3-5% |
| Other (FPGA, networking, custom silicon) | Various | ~8-12% |
AI Chip Foundry Node Allocation
| AI Chip | Vendor | Foundry Node | Notes |
|---|---|---|---|
| Blackwell (B200, GB200) | NVIDIA | TSMC N4P | Mature; volume shipping 2025-2026 |
| Rubin (R100, R200) | NVIDIA | TSMC N3P | Ramp late 2026 / 2027 |
| Rubin Ultra | NVIDIA | TSMC N3P (likely) | 2027 |
| MI300X / MI325X | AMD | TSMC N5P | Mature; volume shipping |
| MI355X / MI400 | AMD | TSMC N3P | 2026 ramp |
| MI450 | AMD | TSMC N3P | Meta first-GW deployment H2 2026 |
| TPU v6 (Trillium) | TSMC N5 | In production | |
| TPU v7 | TSMC N3 | Production ramp | |
| Trainium 2 | AWS | TSMC N5 | In production |
| Maia 2 | Microsoft | TSMC N5 | In production |
| MTIA 2 | Meta | TSMC N5 | In production |
| Apple Neural Engine (M6) | Apple | TSMC N2 | On-device AI |
| Ascend 910C | Huawei | SMIC N+2 (estimated 7nm-class) | China; export-restricted |
TSMC Node Capacity by Generation (Estimated)
| Node | Hsinchu Capacity | Arizona (Phoenix) | Total |
|---|---|---|---|
| N5 / N5P / N4 / N4P | ~165k wafers/mo | ~20k wafers/mo (Fab 21 P1) | ~185k |
| N3 / N3P / N3E | ~125k wafers/mo | ~10k wafers/mo (Fab 21 P2 ramp) | ~135k |
| N2 / N2P (Fab 20) | 60k wafers/mo target Q4 2026 | Not yet | ~60k |
| A16 (next-gen, 2027) | Pilot only 2026 | n/a | n/a |
Strategic Context
Three dynamics shape the 2026 AI chip foundry landscape. First, Apple\u2019s anchor customer position on TSMC leading-edge: Apple\u2019s consistent willingness to pay premium pricing for early access continues to set the economics for the rest of the industry. Second, NVIDIA\u2019s deliberate node choice: keeping Rubin on N3P reflects capacity reality (N2 simply does not have the wafers for Rubin volume in 2026) and economic reality (reticle-stitched giant dies are cheaper to manufacture on a more mature node). Third, the Chinese foundry parallel: SMIC N+2 (7nm-class) production for Huawei Ascend continues to demonstrate that export controls reduce but do not eliminate Chinese frontier-chip capability; the gap to TSMC leading-edge remains approximately three generations.
Brand Visibility Implications
Semiconductor and AI chip coverage drives a large AI assistant query stream from procurement teams, investors, and technical buyers. Brands selling EDA tools, foundry services, IP cores, packaging services, advanced lithography components, and adjacent supply-chain products face strong AI-mediated discovery surface for queries about TSMC, N2 capacity, AI chip foundries, and similar long-tail terms.
Methodology
Capacity and customer allocation data compiled from TSMC investor relations, analyst reports from TrendForce and Mercury Research, and reporting from DigiTimes, Bloomberg, and Reuters. Customer allocation figures are estimated where official disclosures are partial. Updated quarterly with major-customer-announcement events.
How Presenc AI Helps
Presenc AI tracks brand-mention rates on semiconductor and AI chip queries across ChatGPT, Claude, Gemini, and Perplexity. For EDA tool vendors, IP providers, foundry adjacent service brands, and packaging companies, this is the operational visibility into a discovery surface tightly coupled to multi-year procurement and design decisions.