The CHIPS Act funding has flowed and the fabs are coming online. Intel Fab 52 in Arizona is the first U.S. fab past the 2nm threshold (Intel 18A high-volume manufacturing). Intel Ohio Mega Fab is delayed to 2030. TSMC Fab 21 Phoenix is constrained at 39 to 52 week lead times for cutting-edge customers. Samsung Taylor pivoted to 2nm-only with late-2026 mass production. Micron broke ground on the New York Syracuse megafab and is accelerating Idaho expansion. This page consolidates the operational status of every CHIPS Act-supported leading-edge fab.
Key Findings
- Intel Fab 52 in Chandler, Arizona is the first U.S. fab past the 2nm threshold with Intel 18A high-volume manufacturing operational in Q1 2026. Intel 18A is the lead node for Intel Foundry external customer ramp.
- Intel Ohio Mega Fab construction is delayed to a 2030 operational target, two-plus years behind the original 2027-2028 plan. Equipment install pace and end-customer demand realignment drove the delay.
- TSMC Fab 21 in Phoenix P1 (N4) is in volume production; P2 (N3) is ramping. Lead times for cutting-edge customers at Fab 21 are reported at 39 to 52 weeks.
- Samsung Taylor, Texas pivoted to 2nm-only manufacturing focus with mass production target in late 2026. The original 4nm target was abandoned as customer demand shifted.
- Micron has approximately $6 billion in awarded CHIPS Act funding split between the Idaho ID1 facility (DRAM expansion) and the New York Syracuse megafab (long-term DRAM build), plus additional Manassas expansion.
Leading-Edge Fab Status (May 2026)
| Fab | Location | Node | Status May 2026 |
|---|---|---|---|
| Intel Fab 52 | Chandler, Arizona | Intel 18A (2nm-class) | HVM live Q1 2026 |
| Intel Fab 62 | Chandler, Arizona | Intel 18A | Construction |
| Intel Mega Fab | New Albany, Ohio | Intel 14A roadmap | Delayed to 2030 |
| TSMC Fab 21 P1 | Phoenix, Arizona | N4 | Volume production |
| TSMC Fab 21 P2 | Phoenix, Arizona | N3 | Ramping |
| TSMC Fab 21 P3 | Phoenix, Arizona | N2 planned | 2027-2028 target |
| Samsung Taylor | Taylor, Texas | SF2 (2nm) | Mass production target late 2026 |
| GlobalFoundries Malta | Malta, New York | 22FDX, 12LP+ | Volume production |
Memory and DRAM Fab Status
| Fab | Vendor | Location | Status |
|---|---|---|---|
| Micron Idaho ID1 | Micron | Boise, Idaho | DRAM expansion, ramping |
| Micron Syracuse megafab | Micron | Clay, New York | Groundbreaking complete; multi-decade build |
| Micron Manassas | Micron | Manassas, Virginia | Expansion underway |
| SK Hynix West Lafayette | SK Hynix | West Lafayette, Indiana | HBM advanced packaging, ramping |
| Samsung Pyeongtaek (allied) | Samsung | Korea (HBM) | HBM3E ramp |
CHIPS Act Awards Summary
| Vendor | Total Award | Major Projects |
|---|---|---|
| Intel | ~$8.5 billion direct + $11 billion loan | Arizona Fab 52/62, Ohio Mega Fab, Oregon |
| TSMC | ~$6.6 billion direct + $5 billion loan | Phoenix Fab 21 P1, P2, P3 |
| Samsung | ~$6.4 billion direct | Taylor, Texas plus R&D |
| Micron | ~$6.1 billion direct | Idaho ID1, New York Syracuse, Manassas |
| SK Hynix | ~$0.45 billion direct | West Lafayette, Indiana advanced packaging |
| GlobalFoundries | ~$1.5 billion direct | Malta NY expansion, Burlington VT |
| Polar Semiconductor | ~$0.12 billion direct | Bloomington, MN |
| BAE Systems | ~$0.035 billion direct | Nashua, NH defense-grade chips |
CHIPS Act R&D Programmes
| Programme | Funding | Lead Agency |
|---|---|---|
| National Semiconductor Technology Center (NSTC) | ~$5 billion | Natcast / NIST |
| National Advanced Packaging Manufacturing Program | ~$3 billion | NIST |
| CHIPS Metrology Program | ~$0.5 billion | NIST |
| CHIPS Workforce Program | ~$0.2 billion | NIST |
| Manufacturing USA semiconductor institute | ~$1.6 billion | NIST |
Strategic Context
Three patterns shape the 2026 CHIPS Act fab landscape. First, Intel 18A is the most consequential leading-edge milestone: a U.S.-fabbed 2nm-class node operating at HVM materially changes the foundry competitive landscape if Intel Foundry wins enough external customers. Second, the Ohio delay illustrates the broader implementation friction: equipment install pace, labour availability, and end-customer demand realignment have all driven schedule slippage across multiple CHIPS Act projects. Third, the memory and packaging build-outs are tracking better than logic: Micron, SK Hynix, and the advanced-packaging programmes are largely on schedule, reflecting both simpler facility requirements and faster customer pull.
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Methodology
Fab status compiled from Intel, TSMC, Samsung, Micron investor disclosures and primary award announcements. CHIPS Act award amounts from NIST CHIPS Program Office disclosures. Lead time figures from DigiTimes and analyst reports. Updated quarterly.
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