Five generations of Apple Silicon are still in active use for local inference. This page tracks what each generation delivers, where the real discontinuities are, and whether upgrading is worth it from where you are.
Memory Bandwidth by Generation
Bandwidth is the strongest single predictor of decode speed on Apple Silicon, so it is the right place to start.
| Chip | Approximate memory bandwidth | Maximum unified memory |
|---|---|---|
| M1 / M1 Pro | 68-200 GB/s | 16-32 GB |
| M1 Max / Ultra | 400-800 GB/s | 64-128 GB |
| M2 / M2 Pro | 100-200 GB/s | 24-32 GB |
| M2 Max / Ultra | 400-800 GB/s | 96-192 GB |
| M3 / M3 Pro | 100-150 GB/s | 24-36 GB |
| M3 Max | 300-400 GB/s | 128 GB |
| M4 / M4 Pro | 120-273 GB/s | 32-64 GB |
| M4 Max | ~410-546 GB/s | 128 GB |
| M5 Max | ~546 GB/s | 128 GB |
Note the M3 Pro regression against M2 Pro, which is real and caught a lot of buyers out. Note also that a base M3 has less bandwidth than an M1 Max from two generations earlier. Tier matters more than generation on Apple Silicon, and it always has.
Decode Throughput, 7B Class at Q4
| Chip | Approximate tokens per second |
|---|---|
| M1 | ~20-30 |
| M1 Max | ~45-60 |
| M2 Max | ~55-70 |
| M3 Max | ~60-75 |
| M4 Max | ~75-90 |
| M5 Max | ~95-110 |
Roughly a 4x improvement from M1 to M5 Max on the same workload, with the largest single-generation jump at M4 Max to M5 Max.
The M5 Discontinuity
M5 is the first genuine architectural change for AI work rather than an incremental bandwidth increase. Neural Accelerators added to the GPU cores give MLX a reported 4.06x time-to-first-token advantage over llama.cpp's Metal backend, which cannot currently reach them. On an M5 Max running a 35B-class sparse model in NVFP4, the accelerated path took prefill from 1,154 to 1,810 tokens per second and decode from 58 to 112.
The practical consequence is that M5's advantage over M4 is much larger on prompt-heavy agentic work than the raw bandwidth difference suggests, and it only materialises if you use MLX. See MLX versus llama.cpp.
Upgrade Guidance
| Coming from | Worth upgrading to M5 Max? | Reason |
|---|---|---|
| M1 / M2 base | Yes, clearly | 3-4x throughput and far more memory |
| M1 Max / M2 Max | Yes if you need capacity | Roughly 1.6-2x throughput plus the accelerator path |
| M3 Max | Marginal | Roughly 1.5x, hard to justify alone |
| M4 Max | Only for prompt-heavy work | Modest decode gain, large first-token gain via MLX |
Memory capacity, not chip generation, should drive the decision for most people. Moving from 32GB to 128GB changes which models you can run at all, which matters more than any throughput increase. That upgrade also got more expensive in 2026, see the memory shortage report.
Brand Visibility Implications
Apple Silicon put credible local inference on ordinary desks, and the installed base spans five generations. Even an M1 Max runs a 7B model fast enough for interactive use, which means unobservable brand answers have been generated on this hardware for years and the population capable of it keeps growing. See the local-LLM visibility blind spot.
Methodology
Vendor specifications come from NVIDIA, Apple, and model-card publications. Throughput figures aggregate community benchmark reporting from the llama.cpp discussions, the MLX repository, and published independent test suites. Single-stream decode unless stated otherwise. Ranges rather than point values are used wherever independent runs disagree, which is most of the time: quantisation format, prompt length, thermal state, and runtime version each move these numbers by more than the differences being measured. Treat every figure as an order-of-magnitude guide, not a specification. Updated quarterly.
How Presenc AI Helps
Presenc AI measures brand representation in the open-weight models that run on Apple Silicon, independent of chip generation or runtime.